This invention relates generally to testing of integrated circuitry, particularly electronic circuitry incorporating a hardware accelerator block. More particularly, the invention relates to system-on-a-chip circuitry.
Electronic devices employ integrated circuitry. Some complex integrated circuitry, such as system-on-a-chip (xe2x80x9cSOCxe2x80x9d) devices, have at least one processor block and at least one hardware accelerator block. While the processors are programmable to perform various functions, the accelerator blocks are designed to perform a specific function. Rather than perform a particular function on a dataset, a processor may simply send the dataset to an accelerator block for performing the function. This frees the processor to perform functions that cannot be performed by the accelerator blocks. Once the accelerator block has performed the function, it returns the processed dataset to the processor for further use.
In many instances, the SOC design includes, not only circuitry designed by the chip level integrator, but also circuitry designed by other entities (proprietary circuitry). Chip level integrators typically do not have detailed knowledge of the functioning of proprietary circuitry.
Until now, there has been no suitable way to access internal nodes of such circuitry blocks for testing purposes. Data could be examined only before or after a component, such as an accelerator block, processed data. Data could not be examined during the actual processing. This has made it difficult to test and/or understand the workings of some circuitry, particularly proprietary circuitry.
In addition, until now, a hardware system clock has had only two modes, either completely stopped or free running at a relatively high speed, e.g., 30-100 megahertz. This also has made it difficult to test and/or understand the working of such circuitry.
An example of an SOC design is the ARIES device for high speed data transmission in an asymmetric digital subscriber line (ADSL) system manufactured by Lucent Microelectronics. The ARIES device includes two DSP 16000 processor cores and four hardware accelerator blocks. Each processor has its own random access memory (RAM) and read only memory (ROM) and each has an external memory interface (EMI) bus to which hardware accelerators are attached. One DSP 16000 processor core is on the data network side of the chip along with Frame Code Interleaver (FCI) and ATM bridge chip interface (UTOPIA) accelerator blocks. The other processor core is on the client side of the chip along with Fast Fourier Transform (FFT) and multiplexed external memory interface and decimation filter (MEMI) accelerator blocks. The processor cores are manufactured by Lucent Technologies, Inc. and the FCI, UTOPIA, MEMI, and FFT are hardware accelerator blocks are manufactured by entities other than Lucent. Until now, it has been difficult for Lucent, as the chip level integrator, to test and understand the proprietary accelerator blocks which were not designed by Lucent.
Previous troubleshooting techniques included software control of hardware. One class of such techniques, Joint Test Action Group (JTAG) techniques, involves building scan chains into existing circuitry. The technique is used to scan data into and out of blocks, usually through an external JTAG port. In this manner, data could be observed as it entered or exited a block or chip (i.e., at a boundary). Such techniques can be time consuming and difficult and the need for ports and scan chains causes an area penalty on the chip.
In the software context, debugging tools are known for allowing a user to execute software instructions one at a time and to observe the status of external bus signals, such as data and address fields.
The present invention provides a method and apparatus for controlling a clock of a component of an integrated circuit for testing purposes. The clock is controlled on a hardware level. Specifically, a stepped clocking technique is provided by which a processor can advance the clock signal of a component one bit at a time or in rapid bursts of successive bits. This provides for operation of the accelerator block in increments of half-clock cycles (bit by bit). Accordingly, the accelerator block can be stopped during processing of the dataset. Registers of the accelerator block can then be interrogated by the processor, which continues to operate at full clock speed, to determine how the accelerator block is processing the data.